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sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 1 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 30 a vrpower ? integrated power stage description the sic531 and sic531a are integrated power stage solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. packag ed in vishays proprietary 4.5 mm x 3.5 mm mlp package, sic531 and sic531a enable voltage regulator desi gns to deliver up to 30 a continuous current per phase. the internal power mosfets utilize vishays state-of-the-art gen iv trench fet technology that delivers industry benchmark performan ce to significantly reduce switching and conduction losses. the sic531 and sic531a incorporate an advanced mosfet gate driver ic that features high current driving capability, adaptive dead-time control, an integrated bootstrap schottky diode, and zero current detection to improve light load efficiency. the drivers are also compatible with a wide range of pwm controllers, support tri-state pwm, and 3.3 v (sic531a) / 5 v (sic531) pwm logic. features ? thermally enhanced powerpak ? mlp4535-22l package ? vishays gen iv mosf et technology and a low-side mosfet with integrated schottky diode ? delivers up to 30 a continuous current, 35 a at 10 ms peak current ? high efficiency performance ? high frequency operation up to 1.5 mhz ? power mosfets optimize d for 19 v input stage ? 3.3 v (sic531a) / 5 v (sic531) pwm logic with tri-state and hold-off ? zero current detect control for light load efficiency improvement ? low pwm propagation delay (< 20 ns) ? under voltage lockout for v cin ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? multi-phase vrds for computing, graphics card and memory ? intel imvp-8 vrpower delivery ? -v core , v graphics , v system agent skylake, kabylake platforms ? -v ccgi for apollo lake platforms ? up to 18 v rail input dc/dc vr modules typical application diagram fig. 1 - sic531 and sic531a typical application diagram pwm controller g ate driver 5v v in v out v cin zcd_en# pwm v drv v in boot v s wh p g nd g l c g nd pha s e
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 2 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pinout configuration fig. 2 - sic531 and sic531a pin configuration ? ? pin description pin number name function 1 zcd_en# the zcd_en# pin enables or di sables diode emulation. wh en zcd_en# is low, diode emulation is allowed. when zcd_en# is high, continuous conduction mode is forced. zcd_en# can also be put in a high impeda nce mode by floating the pin. if both zcd_en# and pwm are floating, the device shuts down and consumes typically 3 a (9 a max.) current. 2v cin supply voltage for internal logic circuitry 3, 23 c gnd signal ground 4 boot high-side driver bootstrap voltage 5 phase return path of high-side gate driver 6 to 8, 25 v in power stage input voltage. drain of high-side mosfet 9 to 11, 17, 18, 20, 26 p gnd power ground 12 to 16 v swh phase node of the power stage 19, 24 gl low-side mo sfet gate signal 21 v drv supply voltage for internal gate driver 22 pwm pwm input logic ordering information part number package marking code sic531cd-t1-ge3 powerpak ? mlp4535-22l sic531 5 v pwm optimized SIC531ACD-T1-GE3 sic531a 3.3 v pwm optimized sic531adb and sic531d b reference board 1 2 3 4 5 zcd_en# v cin c g nd boot pha s e 16 15 14 13 12 v s wh v s wh v s wh v s wh v s wh 11 10 9 8 7 6 17 18 19 20 21 22 p g nd p g nd p g nd p g nd p g nd g l v drv pwm p g nd v in v in v in p g nd 26 v in 25 c g nd 23 g l 24
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 3 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 part marking information note (1) the specification values indicated ac is v swh to p gnd , -8 v (< 20 ns, 10 j), min. and 30 v (< 50 ns), max. (2) the specification value indicates ac voltage is v boot to p gnd , 36 v (< 50 ns) max. (3) the specification value indicates ac voltage is v boot to v phase , 8 v (< 20 ns) max. ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. ? absolute maximum ratings electrical parameter conditions limit unit input voltage v in -0.3 to 28 v control logic supply voltage v cin -0.3 to 7 drive supply voltage v drv -0.3 to 7 switch node (dc voltage) v swh -0.3 to 28 switch node (ac voltage) (1) -8 to 35 boot voltage (dc voltage) v boot 33 boot voltage (ac voltage) (2) 40 boot to phase (dc voltage) v boot- phase -0.3 to 7 boot to phase (ac voltage) (3) -0.3 to 8 all logic inputs and outputs (pwm and zcd_en#) -0.3 to v cin +0.3 max. operating junction temperature t j 150 c ambient temperature t a -40 to 125 storage temperature t stg -65 to 150 electrostatic disc harge protection human body model, jesd22-a114 3000 v charged device mo del, jesd22-c101 1000 recommended operating range electrical parameter mi nimum typical maximum unit input voltage (v in )4.5-24 v drive supply voltage (v drv ) 4.555.5 control logic supply voltage (v cin ) 4.555.5 boot to phase (v boot-phase , dc voltage) 4 4.5 5.5 thermal resistance from junction to pcb - 5 - c/w thermal resistance from junction to case - 2.5 - = pin 1 indicator p/n = part number code = siliconix logo = esd symbol f = assembly factory code y = year code ww = week code ll = lot code f y w w p/n ll
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 4 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) typical limits are established by characterization and are not production tested. (2) guaranteed by design. electrical specifications ? (zcd_en# = 5 v, v in = 12 v, v drv and v cin = 5 v, t a = 25 c) parameter symbol test condition limits unit min. typ. max. power supply control logic supply current i vcin no switching, v pwm = float - 300 - a f s = 300 khz, d = 0.1 - 300 - drive supply current i vdrv f s = 300 khz, d = 0.1 - 8 15 ma f s = 1 mhz, d = 0.1 - 30 - no switching, v pwm = float - 50 - a bootstrap supply bootstrap diode forward voltage v f i f = 2 ma - - 0.4 v pwm control input (sic531) rising threshold v th_pwm_r 3.4 3.7 4.0 v falling threshold v th_pwm_f 0.72 0.9 1.1 tri-state voltage v tri v pwm = float - 2.3 - tri-state rising threshold v tri_th_r 0.9 1.15 1.38 tri-state falling threshold v tri_th_f 3.1 3.35 3.6 tri-state rising threshold hysteresis v hys_tri_r - 225 - mv tri-state falling threshold hysteresis v hys_tri_f - 325 - pwm input current i pwm v pwm = 5 v - - 350 a v pwm = 0 v - - -350 pwm control input (sic531a) rising threshold v th_pwm_r 2.2 2.45 2.7 v falling threshold v th_pwm_f 0.72 0.9 1.1 tri-state voltage v tri v pwm = float - 1.8 - tri-state rising threshold v tri_th_r 0.9 1.15 1.38 tri-state falling threshold v tri_th_f 1.95 2.2 2.45 tri-state rising threshold hysteresis v hys_tri_r - 225 - mv tri-state falling threshold hysteresis v hys_tri_f - 275 - pwm input current i pwm v pwm = 3.3 v - - 225 a v pwm = 0 v - - -225 timing specifications tri-state to gh/gl rising propagation delay t pd_tri_r no load, see fig. 4 -20- ns tri-state hold-off time t tsho - 150 - gh - turn off propagation delay t pd_off_gh -20- gh - turn on propagation delay (dead time rising) t pd_on_gh -10- gl - turn off propagation delay t pd_off_gl -20- gl - turn on propagation delay (dead time falling) t pd_on_gl -10- pwm minimum on-time t pwm_on_min 30 - - zcd_en# input zcd_en# logic input voltage v ih_zcd_en# input logic high 2 - - v v il_zcd_en# input logic low - - 0.8 protection under voltage lockout v uvlo v cin rising, on threshold - 3.7 4.1 v v cin falling, off threshold 2.7 3.1 - under voltage lockout hysteresis v uvlo_hyst - 575 - mv
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 5 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed operational description pwm input with tri-state function the pwm input receives the pwm control signal from the vr controller ic. the pwm input is designed to be compatible with standard controllers using two state logic (h and l) and advanced controllers that incorporate tri-state logic (h, l and tri-state) on the pwm output. for two state logic, the pwm input operates as follows. when pwm is driven above v pwm_th_r the low-side is turned off and the high-side is turned on. when pwm in put is driven below v pwm_th_f the high-side is turned off and the low-side is turned on. for tri-state logic, the pwm input operates as previously stated for driving the mosfets when pwm is logic high and logic low. however, there is a third state that is entered as the pwm output of tri-state compatible controller enters its high impedance state during shut -down. the high impedance state of the controllers pwm output allows the sic531 and sic531a to pull the pwm input into the tri-state region (see definition of pwm logic and tr i-state, fig. 4). if the pwm input stays in this region for the tri-state hold-off period, t tsho , both high-side and low- side mosfets are turned off. the function allows the vr phase to be disabled without negative output voltag e swing caused by inductor ringing and saves a schottky diode clamp. the pwm and tri-state regions are separated by hysteresis to prevent false triggering. the sic531a incorporates pwm voltage thresholds that are compatible with 3.3 v logic and the sic531 thresholds are compatible with 5 v logic. diode emulation mode (zcd_en#) when zcd_en# pin is logic low and pwm signal switches low, gl is forced on (after normal bbm time). during this time, it is under control of the zcd (zero crossing detect) comparator. if, after the internal blanking delay, the inductor current becomes zero, the low-side is turned off. this improves light load efficiency by avoiding discharge of output capacitors. if pwm enters tri-state, then device will go into normal tri-state mode af ter tri-state delay. the gl output will be turned off regardl ess of inductor current, this is an alternative method of impro ving light load efficiency by reducing switching losses. voltage input (v in ) this is the power input to th e drain of the high-side power mosfet. this pin is conn ected to the high power intermediate bus rail. switch node (v swh and phase) the switch node, v swh , is the circuit power stage output. this is the output applied to the power inductor and output filter to deliver the output for the buck converter. the phase pin is internally connected to the switch node, v swh . this pin is to be used exclusively as the return pin for the boot capacitor. a 20 k ? resistor is connected between gh and phase to provide a discharge path for the hs mosfet in the event that v cin goes to zero while v in is still applied. ? ? ? ground connections (c gnd and p gnd ) p gnd (power ground) should be externally connected to c gnd (signal ground). the layout of the printed circuit board should be such that the inductance separating c gnd and p gnd is minimized. transient di fferences due to inductance effects between these two pins should not exceed 0.5 v. control and drive supp ly voltage input (v drv , v cin ) v cin is the bias supply for th e gate drive control ic. v drv is the bias supply for the gate dri vers. it is recommended to separate these pins through a resistor. this creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the ic. bootstrap circuit (boot) the internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated boot strap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. connect a b oot strap capacitor with one leg tied to boot pin and the other tied to phase pin. shoot-through protection and adaptive dead time the sic531 and sic531a have an internal adaptive logic to avoid shoot through and optimize dead time. the shoot through protection ensures that both high-side and low-side mosfets are not turned on at the same time. the adaptive dead time control operates as follows. the high-side and low-side gate voltages are monitored to prevent the mosfet turning on from tuning on until the other mosfet's gate voltage is suffi ciently low (< 1 v). built in delays also ensure that one power mosfet is completely off, before the other can be turned on. this feature helps to adjust dead time as gate transitions change with respect to output current and temperature. under voltage lockout (uvlo) during the start up cycle, the uvlo disables the gate drive, holding high-side and low-side mosfet gates low, until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. the sic531 and sic531a also incorporate logic to clamp the gate drive signals to zero when the uvlo falling edge triggers the shutdown of the device. as an added precaution, a 20 k ? resistor is connected betwee n gh and phase to provide a discharge path for the hs mosfet.
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 6 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 3 - sic531 and sic531a functional block diagram ???? pwm timing diagram fig. 4 - definition of pwm logic and tri-state device truth table zcd_en# pwm gh gl lll h, i l > 0a l, i l < 0a lhhl l tri-state l l hllh hhhl h tri-state l l pwm v cin c g nd 20k boot v s wh v drv p g nd v ref = 1 v v ref = 1 v anti-cro ss conduction control logic v drv pwm logic control & s tate machine uvlo zcd_en# v in pha s e v cin p g nd g l s w v th_pwm_r v th_pwm_f v th_tri_r v th_tri_f pwm g h g l t pd_off_ g l t t s ho t pd_on_ g h t pd_off_ g h t pd_on_ g l t t s ho t pd_tri_r t pd_tri_r
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 7 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics test condition: v in = 13 v, v drv = v cin = 5 v, zcd_en# = 5 v, v out = 1 v, l out = 250 nh, (dcr = 0.32 m ? ), t a = 25 c ? (all power loss and normaliz ed power loss curves show sic531 and sic531 a losses only unless otherwise stated) fig. 5 - efficiency vs. output current (v in = 12.6 v) fig. 6 - power loss vs . switching frequency (v in = 12.6 v) fig. 7 - efficiency vs. output current (v in = 9 v) fig. 8 - safe operating area (v in = 12.6 v) fig. 9 - power loss vs. output current (v in = 12.6 v) fig. 10 - efficiency vs. output current (v in = 19 v) 62 66 70 74 78 82 86 90 94 0 5 10 15 20 25 30 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + 5 v x (i vdrv + i vcin )] p out = v out x i out , mea s ured at output capacitor 1 mhz 750 khz 500 khz 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 200 300 400 500 600 700 800 900 1000 1100 power lo ss , p l (w) s witching fre q uency, f s (khz) i out = 25a 62 66 70 74 78 82 86 90 94 0 5 10 15 20 25 30 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + 5 v x (i vdrv + i vcin )] p out = v out x i out , mea s ured at output capacitor 1 mhz 750 khz 500 khz 0 5 10 15 20 25 30 35 40 0 153045607590105120135150 output current, i out (a) pcb temperature, t pcb ( c) 1 mhz 500 khz 0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 0 5 10 15 20 25 30 power lo ss , p l (w) output current, i out (a) 750 khz 1 mhz 500 khz 62 66 70 74 78 82 86 90 94 0 5 10 15 20 25 30 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + 5 v x (i vdrv + i vcin )] p out = v out x i out , mea s ured at output capacitor 1mhz 500 khz 750 khz
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 8 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics test condition: v in = 13 v, v drv = v cin = 5 v, zcd_en# = 5 v, v out = 1 v, l out = 250 nh, (dcr = 0.32 m ? ), t a = 25 c ? (all power loss and normaliz ed power loss curves show sic531 and sic531 a losses only unless otherwise stated) fig. 11 - uvlo threshold vs. temperature fig. 12 - pwm threshold vs. temperature (sic531) fig. 13 - pwm threshold vs. temperature (sic531a) fig. 14 - boot diode forward voltage vs. temperature fig. 15 - pwm threshold vs. dr iver supply voltage (sic531a) fig. 16 - pwm threshold vs. driver supply voltage (sic531) 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 -60 -40 -20 0 20 40 60 80 100 120 140 control logic s upply voltage, v cin (v) temperature ( c) v uvlo_fallin g v uvlo_ri s in g 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 -60 -40 -20 0 20 40 60 80 100 120 140 pwm thre s hold voltage, v pwm (v) temperature ( c) v tri_th_r v tri_th_f v tri v th_pwm_r v th_pwm_f 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 -60 -40 -20 0 20 40 60 80 100 120 140 pwm thre s hold voltage, v pwm (v) temperature ( c) v tri_th_r v tri_th_f v tri v th_pwm_r v th_pwm_f 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -60 -40 -20 0 20 40 60 80 100 120 140 boot diode forward voltage, v f (v) temperature ( c) i f = 2 ma 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 pwm thre s hold voltage, v pwm (v) control logic s upply voltage, v cin (v) v th_pwm_f v tri v th_pwm_r v tri_th_f v tri_th_r 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 pwm thre s hold voltage, v pwm (v) control logic s upply voltage, v cin (v) v th_pwm_f v th_pwm_r v tri_th_f v tri_th_r v tri
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 9 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics test condition: v in = 13 v, v drv = v cin = 5 v, zcd_en# = 5 v, v out = 1 v, l out = 250 nh, (dcr = 0.32 m ? ), t a = 25 c ? (all power loss and normaliz ed power loss curves show sic531 and sic531 a losses only unless otherwise stated) fig. 17 - zcd_en# threshold vs. temperature fig. 18 - zcd_en# pull-up current vs. temperature fig. 19 - zcd_en# threshold vs. driver supply voltage fig. 20 - driver quiescent current vs. temperature 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 -60 -40 -20 0 20 40 60 80 100 120 140 zcd_en# thre s hold voltage, v zcd_en# (v) temperature ( c) v il_zcd_en# v ih_zcd_en# -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -60 -40 -20 0 20 40 60 80 100 120 140 zcd_en# pull-up current, i zcd_en# (ua) temperature ( c) v zcd_en# = 0 v 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 zcd_en# thre s hold voltage, v zcd_en# (v) control logic s upply voltage, v cin (v) v ih_zcd_en# v il_zcd_en# 270 290 310 330 350 370 390 410 430 -60 -40 -20 0 20 40 60 80 100 120 140 driver s upply current, i vdvr & i vcin (a) temperature ( c) v pwm = float
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 10 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout recommendations step 1: v in / p gnd planes and decoupling 1. layout v in and p gnd planes as shown above. 2. ceramic capacitors should be placed directly between v in and p gnd , and very close to the device for best decoupling effect. 3. different values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210, 0805, 0603, 0402. 4. smaller capacitance values, pl aced closer to the devices, v in pin(s), results in better high frequency noise absorbing. step 2: v swh plane 1. connect output inductor to ic with large plane to lower resistance. 2. v swh plane also serves as a heat-sink for low-side mosfet. make the plane wide and short to achieve the best thermal path. 3. if any snubber network is required, place the components as shown above and the network can be placed at bottom. step 3: v cin / v drv input filter 1. the v cin / v drv input filter ceramic cap should be placed as close as possible to the ic. it is recommended to connect two capacitors separately. 2. v cin capacitor should be place d between pin 2 and pin 3 (a gnd of driver ic) to achieve best noise filtering. 3. v drv capacitor should be placed between pin 20 (p gnd of driver ic) and pin 21 to provide maximum instantaneous driver current for low side mosfet during switching cycle. 4. for connecting v cin to a gnd , it is recommended to use a large plane to reduce parasitic inductance. step 4: boot resistor and capacitor placement 1. the components need to be placed as close as possible to ic, directly between phase (pin 5) and boot (pin 4). 2. to reduce parasitic inductan ce, chip size 0402 can be used. v in v swh p gnd v in plane p gnd plane p gnd plane v swh snubber p gnd c vcin c vdrv a gnd cboot rboot
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 11 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 step 5: signal routing 1. route the pwm and zcd_en# signal traces out of the top left corner next to pin 1. 2. the pwm signal is an important signal, both signal and return traces should not cr oss any power nodes on any layer. 3. it is best to shield these traces from power switching nodes, e.g. v swh , with a gnd island to improve signal integrity. 4. gl (pin 19) has been conne cted with gl pad (pin 24) internally. ? step 6: adding thermal relief vias 1. thermal relief vias ca n be added on the v in and a gnd pads to utilize inner layers for high-current and thermal dissipation. 2. to achieve better thermal perf ormance, additional vias can be placed on v in plane and p gnd plane. 3. v swh pad is a noise source, it is not recommended to place vias on this pad. 4. 8 mil vias for pads and 10 mils vias for planes are the optimal via sizes. vias on pad may drain solder during assembly and cause assembly issues. consult with the assembly house for guidelines. step 7: ground connection 1. it is recommended to make a single connection between a gnd and p gnd which can be made on the top layer. 2. it is recommended to make the entire first inner layer (below top layer) the ground plane and separate them into a gnd and p gnd planes. 3. these ground planes provide shielding between noise sources on top layer and sign al traces on bottom layer. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p gnd a gnd a gnd v in plane p gnd plane v swh p gnd v in a gnd v swh p gnd a gnd
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 12 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern powerpak ? mlp4535-22l component for mlp 4.5 x 3.5 22l land pattern for mlp 4.5 x 3.5 22l 22 21 20 19 18 17 6 7 8 9 10 11 1 2 3 4 5 16 15 14 13 12 0.75 0.75 0.37 0.30 0.30 0.75 1 0.5 x 2 = 1.00 0.5 x 3 = 1.50 0.5 x 4 = 2.00 0.75 0.75 2.31 0.145 0.75 0.595 0.45 0.14 0.45 0.75 0.50 0.30 0.595 0.30 0.5 x 2 = 1.00 0.30 3.50 3.050 0.210 0.365 0.355 0.110 45 0.810 0.31 0.145 12.00 0.3 1.610 0.145 0.895 0.555 2.05 0.190 1.16 1.205 0.735 0.290 5 135 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0.30 0.75 4.50 0.45 0.155 1.00 3 2 1 0.5 x 4 = 2.00 0.150 0.80 0.25 c 0.114 c 0.114 0.140
sic531, sic531a www.vishay.com vishay siliconix s15-2799-rev. a, 30-nov-15 13 document number: 65999 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline drawing mlp4535-22l ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65999 . dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.0029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.0078 0.0098 0.0110 d 4.50 bsc 0.177 bsc e 0.50 bsc 0.019 bsc e 3.50 bsc 0.137 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 22 22 nd (3) 66 ne (3) 55 d1-1 0.35 0.40 0.45 0.013 0.015 0.017 d1-2 0.15 0.20 0.25 0.005 0.007 0.009 d2-1 1.02 1.07 1.12 0.040 0.042 0.044 d2-2 1.02 1.07 1.12 0.040 0.042 0.044 d2-3 1.47 1.52 1.57 0.057 0.059 0.061 d2-4 0.25 0.30 0.35 0.009 0.011 0.013 e1-1 1.095 1.145 1.195 0.043 0.045 0.047 e1-2 2.67 2.72 2.77 0.105 0.107 0.109 e1-3 0.35 0.40 0.45 0.013 0.015 0.017 e1-4 1.85 1.90 1.95 0.072 0.074 0.076 e1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076 e2-1 3.05 3.10 3.15 0.120 0.122 0.124 e2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458 e2-3 0.695 0.745 0.795 0.027 0.029 0.031 e2-4 0.40 0.45 0.50 0.015 0.017 0.019 k1 0.40 bsc 0.015 bsc k2 0.07 bsc 0.002 bsc k3 0.05 bsc 0.001 bsc k4 0.40 bsc 0.015 bsc 9 14 1 11 10 5 4 3 2 16 17 19 8 22 7 15 20 21 6 13 18 12 9 14 1 11 10 5 4 3 2 16 17 19 8 22 7 15 20 21 6 13 18 12 d e a a1 a2 b e l d2-1 d2-2 d2-3 d2-4 e2-1 e2-2 e2-3 e2-4 k1 k2 a pin 1 dot by marking c 56 b k3 d1-1 e1-1 e1-2 d1-2 k4 e1-4 e1-3 e1-5 0.1 c b 2x 0.1 c a 2x 0.08 c
package information www.vishay.com vishay siliconix revision: 20-oct-14 1 document number: 67234 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 mlp 4.5 x 3.5-22l bwl case outline dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.0029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.0078 0.0098 0.0110 d 4.50 bsc 0.177 bsc e 0.50 bsc 0.019 bsc e 3.50 bsc 0.137 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 22 22 nd (3) 66 ne (3) 55 d1-1 0.35 0.40 0.45 0.013 0.015 0.017 d1-2 0.15 0.20 0.25 0.005 0.007 0.009 d2-1 1.02 1.07 1.12 0.040 0.042 0.044 d2-2 1.02 1.07 1.12 0.040 0.042 0.044 d2-3 1.47 1.52 1.57 0.057 0.059 0.061 d2-4 0.25 0.30 0.35 0.009 0.011 0.013 e1-1 1.095 1.145 1.195 0.043 0.045 0.047 e1-2 2.67 2.72 2.77 0.105 0.107 0.109 e1-3 0.35 0.40 0.45 0.013 0.015 0.017 e1-4 1.85 1.90 1.95 0.072 0.074 0.076 e1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076 e2-1 3.05 3.10 3.15 0.120 0.122 0.124 e2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458 e2-3 0.695 0.745 0.795 0.027 0.029 0.031 e2-4 0.40 0.45 0.50 0.015 0.017 0.019 k1 0.40 bsc 0.015 bsc k2 0.07 bsc 0.002 bsc k3 0.05 bsc 0.001 bsc k4 0.40 bsc 0.015 bsc 9 14 1 11 10 5 4 3 2 16 17 19 8 22 7 15 20 21 6 13 18 12 9 14 1 11 10 5 4 3 2 16 17 19 8 22 7 15 20 21 6 13 18 12 d e a a1 a2 b e l d2-1 d2-2 d2-3 d2-4 e2-1 e2-2 e2-3 e2-4 k1 k2 a pin 1 dot by marking c 56 b k3 d1-1 e1-1 e1-2 d1-2 k4 e1-4 e1-3 e1-5 0.1 c b 2x 0.1 c a 2x 0.08 c
package information www.vishay.com vishay siliconix revision: 20-oct-14 2 document number: 67234 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes 1. use millimeters as the primary measurement 2. dimensioning and tolerances conform to asme y14.5m. - 1994 3. n is the number of terminals, nd is the number of terminals in x-direction and ne is the number of terminals in y-direction. 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals t14-0626-rev. a, 20-oct-14 dwg: 6028
pad pattern www.vishay.com vishay siliconix revision: 05-nov-14 1 document number: 66914 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern powerpak ? mlp4535-22l land pattern package outline top view, tran s parent (not bottom view) all dimen s ion s in millimeter s 22 21 20 19 18 17 22 21 20 19 18 17 678 91011 678 91011 1 2 3 4 5 16 15 14 13 12 16 15 14 13 12 4.5 (d2-4) 0.3 (d1-2) 0.2 (k4) 0.4 (d2-1) 1.07 (k1) 0.4 (d1-1) 0.4 (d2-2) 1.07 (d2-3) 1.52 (l) 0.4 (k2) 0.07 (k3) 0.05 (e1-2) 2.72 (e2-2) 1.11 (e1-1) 1.15 (e2-3) 0.75 (e) 0.5 1 2 3 4 5 (d1-5) 0.14 (e1-4) 1.9 (e1-3) 0.4 (e2-4) 0.45 3.5 3.5 (e2-1) 3.1 (b) 0.25 3.05 0.75 0.3 0.75 0.5 x 4 = 2 0.29 0.21 0.37 0.3 0.3 0.5 x 4 = 2 0.75 0.75 0.59 0.14 4.5 0.75 1 0.5 0.75 0.3 0.5 x 3 = 1.5 0.3 0.45 0.45 0.31 0.75 0.75 1 0.5 x 2 = 1 0.5 x 2 = 1 0.3 0.1 0.9 0.37 1.2 0.29 0.74 0.3 0.55 0.5 0.29 1.16 1.61 0.25 0.8 0.3 0.3 0.4 0.36 2.05 22 21 20 19 18 17 678 91011 1 2 3 4 5 16 15 14 13 12
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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